This invention relates to a semiconductor device manufacturing method and a semiconductor device.
A technique for three-dimensionally arranging memory cells is proposed in, for instance, JP-A-2007-266143 (Kokai). In this technique, a plurality of electrode layers functioning as control gates in a memory device are stacked alternately with insulating layers to form a multilayer body. Memory holes are formed therein, and a charge storage layer is formed on the inner wall of the memory hole. Then, silicon is provided in the memory hole.
This results in a structure in which the electrode layers cover the pillar-shaped silicon at a prescribed pitch, and a memory cell is formed at each intersection between the electrode layer and the silicon pillar. The memory hole is formed through the multilayer body of a plurality of electrode layers and a plurality of insulating layers. Here, as the number of stacked layers increases and the aspect ratio of the memory hole becomes higher, the sidewall of the memory hole is tapered, and the hole diameter tends to decrease toward the bottom of the memory hole. Variation in the hole diameter along the depth of the memory hole may lead to variation in the characteristics of memory cells between the upper-layer side and the lower-layer side.